1. Field of the Invention
The present invention relates to the design of semiconductor integrated circuits. In particular, this invention is related to the architectural design of semiconductor integrated circuits having a large integration of memory cells such as Read Only Memory (ROM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Electrically Programmable Read Only Memory (EPROM), Electrically Erasable Programmable Read Only Memory (EEPROM), and flash EEPROM.
2. Description of the Related Art
With the rapid advance in semiconductor processing technologies, semiconductor memories are widely used for the implementation of large scale memory systems. Semiconductor memories are generally classified into two types, namely, the volatile type and the non-volatile type. Examples of volatile memories are SRAM and DRAM, in which the stored data are lost in conjunction with the loss of power. While for non-volatile memories, such as ROM, EPROM and EEPROM, stored data remain with the memory cells irrespective of whether power is on or off.
There are various kinds of semiconductor memory integrated circuits with different structures and characteristics. The most commonly used are the types in which each memory cell comprises three terminals. The three terminals are respectively the source, the drain and the gate of a conventional Metal Oxide Semiconductor Field Effect Transistor (MOSFET). Take the example of a non-volatile memory circuit such as a ROM. Pre-programmed low and high threshold voltages of the MOSFET within each ROM cell correspond to the digital bits "0" and "1" stored in a ROM circuit. As yet another example, in the case with EPROM, EEPROM, or flash EEPROM, in which each memory cell includes a floating gate disposed atop a MOSFET, the threshold voltage of the MOSFET is programmable via the floating gate. Addressing of such conventional memory circuits usually involves the partition of N address lines into two groups. FIG. 1a shows such a structure. For example, the first group is labeled as A.sub.0, A.sub.1, A.sub.2, . . . , A.sub.i-1, while the second group is identified as A.sub.i, A.sub.i+1, A.sub.i+2, . . . , A.sub.N-1, where i is an integer. The first group of address lines, A.sub.0, A.sub.1, A.sub.2, . . . , A.sub.i-1, are used to drive one of the x wordlines WL.sub.0, WL.sub.1, WL.sub.2, . . . , WL.sub.x-1 through a row decoder, for example, in which x and i are related by the mathematical expression: x=2.sup.i. The second group of address lines, A.sub.i, A.sub.i+1, A.sub.i+2, . . . , A.sub.N-1, are used to select one of the y vertical bitlines, BL.sub.0, BL.sub.1, BL.sub.2, . . . , BL.sub.y-1, through a column decoder, for example, in which y and i are related by the mathematical expression: y=2.sup.N-i. Such an addressing scheme is especially suitable for a memory array with three-terminal storage elements. Normally, the drain terminals of the MOSFETs in a column of the matrix of memory cells are tied together to form the bitlines, while the gate terminals of the MOSFETs in a row of the matrix are tied together to form wordlines. FIG. 1b is a general schematic representation of a three-terminal storage element which may comprise either one of the memory cells as shown in FIG. 1c or FIG. 1d. FIG. 1c is a schematic representation of a ROM cell, and FIG. 1d is another schematic representation of a EPROM, EEPROM or a flash EEPROM cell. It should be noted that shown in FIG. 1a is only the core of the memory array in a matrix of rows and columns. There are also row and column decoders used for the addressing of each of the memory cells, not shown in FIG. 1a, as were mentioned previously. Alternatively, another control line can be added to the aforementioned array. The additional control line is tied to the substrate, such that the substrate of the memory cells can be raised to a predetermined voltage level for a fast sector erasure. Details of such a memory circuit can be found in a technical publication by Jinbo et al., entitled "A 5 V-Only 16 Mb Flash Memory with Sector-Erase Mode", IEEE Journal of Solid-State Circuits, Vol. 27, No. 11, November 1992, pp 1547-1553.
In an effort to increase the integration density, there are memory circuits that link the memory cells together in a NAND structure, in which the informational bits are stored serially. Such type of circuits can be found in another technical publication by Shirota et al., entitled "A 2.3 um.sup.2 Memory Cell Structure for 16 Mb NAND EEPROM", IEDM 1990, Technical Digest, pp 103-106; and also in Momodomi et al., entitled "New Device Technologies for 5 V only 4 Mb EEPROM with NAND Structure Cell", IEDM 1988, Technical Digest, pp 412-415.
To facilitate the addressing of memory circuits with large main arrays, there are circuits designed in the past which divide the address lines into three groups. This is in contrast with the conventional memory circuits in which two groups of address lines are partitioned respectively for the wordlines and the bitlines. The additional group of address lines is used to address the many sub-arrays partitioned from the main array, or for the addressing of the pre-divided groups of wordlines. An example of such memory circuit can be found in Yiu, U.S. Pat. No. 5,117,389, entitled "Flat-Cell Read-Only-Memory Integrated Circuit", May 26, 1992. In Yiu, the memory circuit includes control and select transistors for each sub-array. The control and select transistors are interposed with the memory cells in the memory core. FIG. 2 shows a schematic of such a circuit. As is shown, wordlines are labeled SWL.sub.N1, SWL.sub.N2, . . . , SWL.sub.NM, while bitlines are labeled BL.sub.N, BL.sub.N+1. Virtual ground lines are identified as VG.sub.N and VG.sub.N+1, and the sub-array select lines are labeled as BWL.sub.N and BWL.sub.N+1
Memory circuits of the aforementioned types involve very complicated addressing schemes. Typically, an entire column or an entire row of memory cells in the main array are first addressed. The addressed column or row is then individually decoded for reading or programming. The associated addressing circuitries are complicated in design. Equally as undesirable, memory addressing speed is penalized as several timing cycles are involved in the accessing of the individual memory cells.